Similar to a redundancy saving technique for a defective memory cell of a nonvolatile storing device and a volatile semiconductor storing device such as a DRAM, various kinds of methods have been proposed and implemented. As a generally used redundancy saving technique, there is a method in which a defective row or a defective column containing a defective memory cell in a memory cell array, or a totally defective row or column is replaced with a redundant row or a redundant column that is prepared in some numbers in the vicinity of the memory cell array previously. In this case, a defective row address and a defective column address are stored in defective address storing means, and the stored defective row address and defective column address are compared with an address transmitted from outside and when they coincide with each other, a redundant row or a redundant column is automatically selected.
Although the row or column saving is an effective saving method when a defective mode is generated by the memory cell unit or in a row direction or a column direction, the row or the column that can be saved is limited depending on the number of the redundant rows or the redundant columns. Thus, the above saving is not effective in a multi-bit sequential defects (a plurality of defective memory cells become defective in sequential block) due to a particle, which is more frequently generated as a manufacturing process is miniaturized.
Thus, there is a block redundancy saving method in which a memory block including a certain unit of memory cells is saved in block. The above block redundancy saving method can effectively save the multi-bit sequential defect due to the particle and the like, so that a manufacturing yield can be improved.
Here, as a method for converting a defective address to a redundant address that can be applied to the block redundancy saving method, there is an address translation method proposed in a “semiconductor integrated circuit device” disclosed in Patent Document 1. According to the address translation method, a memory section having a memory cell array in which memory cell array columns having capacity exceeding capacity of a range selected by an address are arranged and an address translation circuit converting an address and selecting a memory cell of the memory section are provided, and correspondent relation between addresses and memory cell columns are fixed so that the address translation circuit replaces memory cell columns a number of which is more than defective memory cell columns including defective memory cell columns with the other normal memory cell columns. That is, an address translation pattern is fixedly stored by a fuse, so that it becomes not necessary to confirm coincidence or dissidence of the defective address every time an address is inputted. However, according to the address translation method, since row or column saving is assumed originally, when a plurality of redundant rows or redundant columns are to be related to a plurality of redundant blocks, a plurality of defective memory blocks can be saved at high speed without using address comparing means, however in this case, it is necessary to mount many redundant blocks on a chip previously, or a block that is not used is generated in a normal memory block, causing actual usage efficiency to be lowered and a memory bit cost to be increased.
Patent Document 1: Japanese Unexamined Patent Publication No. 2001-256793